Connected component analysis is one of the most fundamental steps used in several image\nprocessing systems. This technique allows for distinguishing and detecting different objects in images\nby assigning a unique label to all pixels that refer to the same object. Most of the previous published\nalgorithms have been designed for implementation by software. However, due to the large number of\nmemory accesses and compare, lookup, and control operations when executed on a general-purpose\nprocessor, they do not satisfy the speed performance required by the next generation high performance\ncomputer vision systems. In this paper, we present the design of a new Connected Component Labeling\nhardware architecture suitable for high performance heterogeneous image processing of embedded\ndesigns. When implemented on a Zynq All Programmable-System on Chip (AP-SOC) 7045 chip,\nthe proposed design allows a throughput rate higher of 220 Mpixels/s to be reached using less than\n18,000 LUTs and 5000 FFs, dissipating about 620 �¼J.
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